We are seeking an experienced RTL Design Engineer to work on next-generation
wireless SoC development. The ideal candidate will design and implement
high-performance digital blocks and work closely with architecture,
analog/mixed-signal, and verification teams to deliver production-quality
silicon.
? Key
Responsibilities
Design,
implement, and verify digital blocks for wireless SoCs using
SystemVerilog/Verilog
Translate
architectural and algorithmic specifications into synthesizable RTL
Implement
DSP blocks such as filtering, FFT/IFFT, beamforming, etc.
Develop
RTL for SoC components including interfaces, clock/reset, power
management, and debug logic
Work
with internal and external IP integration into chip-level designs
Collaborate
with AMS teams on digital-analog interfaces, calibration logic, and
control systems
Drive
PPA (power, performance, area) optimization and support timing closure
with backend teams
Participate
in design reviews, integration, synthesis, and timing closure activities
Support
silicon bring-up and lab validation of digital subsystems
? Required
Skills
5+
years of hands-on RTL design experience (SystemVerilog / Verilog)
Strong
understanding of micro-architecture and RTL implementation from specs
Experience
in DSP hardware implementation (filtering, FFT, etc.)
Knowledge
of SoC design flows: CDC, power domains, timing constraints, formal
verification
Experience
with synthesis, linting, simulation, and STA tools
Understanding
of DFT concepts (scan, BIST)
Strong
debugging and problem-solving skills
Good
communication and ability to work in cross-functional teams
? Preferred
Skills
Experience
in wireless SoC domains (Wi-Fi, cellular, mmWave, satellite, etc.)
RTL
design of datapath, FIFO, DMA, arbitration, and SoC bus (AXI/AHB)
