Strong hands-on
experience in ASIC DFT with end-to-end ownership.
Solid
understanding of DFT fundamentals, fault models, test techniques, and test
coverage concepts.
Deep expertise
in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon
debug.
Hands-on
experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven
experience in scan insertion, ATPG setup, simulation, debug, and DRC
analysis.
Experience with
MBIST implementation and verification; SMS experience preferred.
Experience with
scan architecture and scan chain stitching; Tessent/SSN experience
preferred.
Strong
understanding of PLLs, RTL design, synthesis flows, logical equivalence
checking (LEC), and physical design implementation.
Proven
post-silicon debug and silicon bring-up experience.
Exposure to
large SoC designs, hierarchical DFT flows, and multi-domain integration
challenges.
Strong
communication skills and the ability to work independently with minimal
ramp-up.
Preferred
Experience
MBIST
post-silicon validation.
ATPG simulations
and fault coverage debug.
DFT RTL, DFD,
DFT verification, and IP-level DFT integration.
DFT SDC creation
and DFT timing closure support.
Boundary scan,
iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL
scripting for DFT automation, reporting, and debug.
Experience
working across multiple ASIC technology nodes and complex product
development cycles.
Familiarity with
yield learning, diagnosis, and manufacturing test optimization.
Information
Locations San Jose, CAPosition Open to Anywhere in the US, but will work on-siteIndustry ManufacturingStatus OpenJob Age 41 Day'sCreated Date 05/07/2026No.of Positions 1Duration 12Zip Code
