10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary
We are seeking a highly experienced Lead ASIC DFT Engineer to
architect, implement, verify, and debug advanced DFT solutions for complex ASIC
and SoC designs. This role requires deep technical ownership across DFT
architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and
post-silicon validation, along with the ability to lead cross-functional debug
efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals,
fault models, test coverage, diagnosis, and debug, as well as the ability to
evaluate and adopt emerging DFT methodologies and architecture schemes to
improve robustness, quality, and yield.
Key Responsibilities
Lead
DFT architecture, implementation, verification, and sign-off for complex
ASIC and SoC designs.
Drive
scan architecture, scan insertion, scan chain stitching, and scan
compression workflows to achieve high coverage and robust testability.
Own
MBIST/LBIST integration, implementation, verification, and debug across
design and silicon bring-up phases.
Perform
DFT debug, failure analysis, root-cause investigation, and fault coverage
closure for complex silicon issues.
Develop
and validate DFT constraints, including DFT SDC, timing checks, and
DFT-specific timing analysis.
Collaborate
with RTL design, verification, physical design, STA, and silicon
validation teams to resolve integration and implementation issues.
Support
ATPG pattern generation, ATPG simulations, DRC analysis, test coverage
analysis, and diagnosis/debug.
Work
on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review
RTL, synthesis, LEC, and physical design impacts on DFT implementation and
test quality.
Act
as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor
junior and mid-level DFT engineers and promote best practices in DFT
methodology and automation.
Develop
scripts and automation using TCL, PERL, or Python to improve flow
efficiency and debug productivity.
Required Skills & Qualifications
Strong
hands-on experience in ASIC DFT with end-to-end ownership.
Solid
understanding of DFT fundamentals, fault models, test techniques, and test
coverage concepts.
Deep
expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan,
and silicon debug.
Hands-on
experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven
experience in scan insertion, ATPG setup, simulation, debug, and DRC
analysis.
Experience
with MBIST implementation and verification; SMS experience preferred.
Experience
with scan architecture and scan chain stitching; Tessent/SSN experience
preferred.
Strong
understanding of PLLs, RTL design, synthesis flows, logical equivalence
checking (LEC), and physical design implementation.
Proven
post-silicon debug and silicon bring-up experience.
Exposure
to large SoC designs, hierarchical DFT flows, and multi-domain integration
challenges.
Strong
communication skills and the ability to work independently with minimal
ramp-up.
Preferred Experience
MBIST
post-silicon validation.
ATPG
simulations and fault coverage debug.
DFT
RTL, DFD, DFT verification, and IP-level DFT integration.
DFT
SDC creation and DFT timing closure support.
Boundary
scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL
scripting for DFT automation, reporting, and debug.
Experience
working across multiple ASIC technology nodes and complex product
development cycles.
Familiarity
with yield learning, diagnosis, and manufacturing test optimization.
Information
Locations Position Open to RemoteIndustry ManufacturingStatus OpenJob Age 15 Day'sCreated Date 06/02/2026No.of Positions 1Duration 12Zip Code
